1. Field of the Invention
The invention relates to logic circuits. More particularly, the invention relates to logic circuits with dynamic latches or logic.
2. Description of Related Art
Computers, phones, radios, televisions, and other electronic products are becoming more powerful and less expensive as more and more circuitry is compressed into logic circuits. Logic circuits are used for a wide variety of applications including delay registers, counters, processors, digital signal processors/filters, accumulators, pipelined arithmetic circuits, state machines, data storage registers, and other clocked circuits. A basic component of most logic circuits used today is complementary metal oxide silicon (CMOS) latches or logic. Latches are typically used to store data while the data is manipulated by other circuit logic. CMOS latches are generally designed as either dynamic or static.
A dynamic latch is smaller, faster, and more energy efficient than a static latch. Accordingly, the dynamic latch is an attractive design choice and has become the preference of circuit designers. As is known in the art, a dynamic latch can be designed with many different structures, including those disclosed in U.S. Pat. No. 5,606,270 to D'Souza et al. Typically, a dynamic latch can be implemented with only four CMOS transistors, whereas a corresponding static latch requires at least ten transistors. In other words, the typical dynamic latch is less than half the size of the static latch. Fewer CMOS transistors also equate to less loading (e.g., capacitance) on the dynamic latch. Thus, dynamic latches can operate approximately twice as fast as static latches. Less loading also means that dynamic latches require less power supply current to drive the load, thus require less power (better energy efficiency).
Notwithstanding the foregoing advantages, logic circuits with dynamic latches are problematic in certain instances. Namely, problems arise during test, reset, and power down operations.
As is well known, dynamic latches must be continually clocked (refreshed) in order to operate properly (static latches have extra transistors to retain the stored values permanently and thus do not require refreshing). As the name "dynamic" implies, the storage state of a latch will change with time and thus needs to be refreshed. This is generally not an issue during normal circuit operation because a clock is always available for refreshing.
One problem is that during test, reset, and power down operations a clock is typically not available. In other instances it is also desirable to turn the clock off in order to conserve power. Without a clock for refreshing, dynamic latches slowly change states and/or lose the stored values.
Another problem is "through currents." This well known condition occurs because a CMOS gate becomes effectively a short circuit between power and ground whenever its input values transition between high and low states. Without a clock, a dynamic latch's storage node will remain in the transition region for an extended period of time, thereby causing the CMOS gates following the dynamic latch to become short circuits for exceedingly long periods of time.
The testing of logic circuits including dynamic latches is accordingly difficult. Circuit testers generally require stopping or stalling a test in progress to take measurements of power supply currents, input leakage currents, and output voltage levels. When a test is stopped, the clock is also stopped, and the dynamic latches eventually cause "through currents" which disturb the measurements. Special test equipment or test procedures must be used to mitigate this problem.
The reset of logic circuits with dynamic latches is also a problem. It is generally desirable to be able to reset a logic circuit when not in use or when the circuit is not being clocked. For example, a logic circuit with dynamic latches may be mounted on a module that will receive its clock from a source which is not on the module. In this instance, the logic circuit will not receive a clock until the clock source is ready. When this occurs, the dynamic latches will begin causing through currents, greatly increasing the power consumption of the module.
In addition, it is generally desirable to power down a logic circuit when not in use to reduce power consumption. Because logic circuits draw current whenever clocked, it is desirable to turn off the clock when the logic circuit is not in use. This is not possible with dynamic latches because the resultant through current will actually increase the power consumption of the circuit.
One disadvantage of conventional solutions is that the logic circuit is not placed into a fully static mode. For example, extra circuitry can be used to generate an alternate clock (with a frequency much lower than that of the clock used for refreshing) for use once the clock of the logic circuit is stopped. See, e.g., U.S. Pat. No. 5,587,672 to Ranganathan et al. Since this type of solution does not make the logic circuit fully static, the circuit continues to draw power and further complicates testing.
Another disadvantage of conventional solutions is that they require considerable size and complexity to implement. For example, one such solution requires "back bias" dynamic circuits to reduce or eliminate leakage that causes dynamic storage nodes to lose their charge. See, e.g., U.S. Pat. No. 5,550,487 to Lyon. Another solution requires "self reverse biasing" circuitry to eliminate or reduce the leakage. See, e.g., U.S. Pat. No. 5,606,270 to D'Souza et al. Conventional solutions also require gates for driving dynamic nodes when the latches are not clocked. See, e.g., U.S. Pat. No. 5,557,620 to Miller, Jr. et al.